Adisyn Adds Another Layer to Its Graphene Patent Shield

Adisyn has strengthened its United States intellectual property position after the US Patent and Trademark Office allowed a second patent application covering graphene-coated products intended for next-generation semiconductor applications.

The latest allowance relates to graphene-coated three-dimensional surfaces, including semiconductor interconnects with defined physical and purity characteristics. It complements the company’s earlier US patent allowance, disclosed in May 2026, which covered a method for applying tethered graphene coatings to metallic surfaces as well as the resulting products and devices.

For investors, the important distinction is that the new claims are focused on the characteristics of the finished product rather than being restricted to Adisyn’s particular manufacturing process.

That could make the protection harder to sidestep.

A competing manufacturer may potentially use different precursors, equipment or production techniques, but could still fall within the patent claims if its finished graphene-coated surface displays the protected specifications.

Patents are never an automatic ticket to commercial success, but product-based claims can provide a broader defensive perimeter than process claims alone. Adisyn is effectively seeking protection for both the recipe and selected characteristics of the meal.

What the patent claims cover

The allowed claims apply to uniform and conformal graphene coatings deposited over complex three-dimensional geometries.

The protected products may also include copper interconnects with a median grain size below 0.9 microns, fewer shorts and voids following exposure to temperatures of at least 400 degrees Celsius, or metal that is substantially free of conventional diffusion barrier coating materials.

The claims also cover graphene coatings without nitrogen doping, iron chloride residuals or remaining metal catalyst nanoparticles.

These details matter because semiconductor interconnects are the microscopic wiring structures that carry electrical signals within a chip. As processors become smaller and more densely packed, copper interconnects encounter rising electrical resistance, heat and reliability challenges.

Adisyn is developing a low-temperature atomic layer deposition process intended to grow graphene directly on semiconductor wafers. The company believes graphene could improve the performance of copper interconnects while reducing or removing the need for conventional diffusion barriers.

Those barriers help prevent copper from migrating into surrounding materials, but they also occupy valuable space. At advanced semiconductor dimensions, every sliver of room counts.

Managing director Arye Kohavi said copper grain size and reductions in shorts and voids could affect electrical resistivity and thermal performance. He also noted that removing conventional diffusion barrier materials could create additional space as processors continue to scale.

A layered defence rather than a single patent bet

Adisyn’s intellectual property strategy extends beyond registered patents. The company is retaining some technical knowledge as trade secrets, including proprietary processes, operational expertise and accumulated manufacturing know-how.

That approach is common in emerging technology fields. A patent provides enforceable rights in exchange for public disclosure, while trade secrets protect information that may be more valuable when kept behind closed laboratory doors.

The combination may become increasingly important as Adisyn moves from research towards process scale-up and discussions with potential commercial partners.

The May allowance protected a graphene coating method and its outputs. The latest allowance adds claims centred on the physical properties of the coated products. Together, they provide overlapping protection across how the technology is produced and what the resulting product looks like.

The company is also assessing additional patent filings in other jurisdictions, suggesting its intellectual property strategy remains a work in progress rather than a completed portfolio.

Commercial proof remains the next hurdle

The allowance is strategically useful, but investors should distinguish intellectual property progress from commercial validation.

Adisyn has not disclosed a semiconductor manufacturing contract, licensing agreement or revenue forecast arising from the patent. Nor has it provided economic details covering production costs, manufacturing yields or the capital required to scale the technology.

Those are critical issues in semiconductor materials development, where an impressive laboratory result must still survive rigorous qualification, integration and high-volume manufacturing requirements.

The company said it is progressing engagement with potential partners and customers across its semiconductor interconnect program and its separate radar signature reduction business.

That second application involves advanced composite materials intended to reduce radar signatures in unmanned aerial vehicles and defence platforms. While both programs draw on Adisyn’s graphene expertise, they address very different markets and commercial pathways.

The latest patent allowance therefore improves the company’s strategic position without removing the execution risk. The investment case will increasingly depend on whether Adisyn can convert its expanding intellectual property portfolio into industry partnerships, funded development programs or commercial agreements.

For now, the company has added another layer to its graphene armour. The harder task is proving there is a paying customer waiting on the other side.