Adisyn Extends Graphene Patent Protection to Non-Metallic Semiconductor Surfaces

Adisyn has strengthened its intellectual property position in semiconductor graphene technology after the United States Patent and Trademark Office allowed a third US patent application, this time covering the deposition of graphene directly onto non-metallic surfaces.

The application, titled Method for Coating a Non-Metallic Surface with Graphene, extends the company's protection beyond the metallic surfaces covered by its earlier US patent allowances. The significance is that modern semiconductor interconnects contain both conductive metals and surrounding non-metallic dielectric materials, so Adisyn is progressively building protection across both sides of a critical interface.

The allowed claims cover a process using a graphene molecular precursor capable of forming a covalent bond directly with a non-metallic surface. Importantly for semiconductor manufacturing, the process maintains the underlying surface below 400°C, supporting Adisyn's broader strategy of developing low-temperature graphene deposition processes suitable for semiconductor environments.

Covering both sides of the interconnect

The commercial logic behind the patent becomes clearer when looking at how semiconductor interconnects are constructed.

Copper wiring carries electrical signals through a chip, while a barrier layer is used to prevent copper atoms migrating into the surrounding dielectric material. That dielectric material provides electrical insulation and is predominantly non-metallic.

Traditional barrier layers can use compounds such as tantalum nitride. Adisyn's technology is aimed at using graphene as an alternative barrier material.

The newly allowed claims protect the deposition of graphene onto the non-metallic dielectric surface, complementing earlier intellectual property covering graphene deposition onto metallic surfaces and resulting metal-based interconnect products.

This effectively gives Adisyn protection from two directions: graphene interacting with the conductive metal and graphene interacting with the surrounding dielectric.

That does not guarantee commercial adoption, of course, but from an intellectual property perspective it gives the company broader coverage around the architecture it ultimately hopes semiconductor manufacturers will use.

The battle against the semiconductor 'barrier tax'

The technical opportunity is driven by an increasingly awkward problem for advanced chipmakers.

As semiconductor architectures shrink below 5 nanometres, the available space for interconnect wiring becomes extremely constrained. Yet the barrier and dielectric materials surrounding those wires cannot simply disappear because they perform essential containment and insulation functions.

The result is what Adisyn describes as the "barrier tax" - a growing proportion of extremely valuable chip real estate being consumed by materials that protect the wiring rather than conduct electricity.

Graphene's potential attraction is its extreme thinness. Adisyn has previously demonstrated its ability to deposit graphene at approximately 1 nanometre thickness.

If graphene-based barriers can ultimately perform the required diffusion-barrier function at significantly reduced thickness, chip designers could potentially free up more space within increasingly cramped interconnect structures.

The latest claims specifically